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HAL and API libraries for MCUs and hardware.
stm32f103cb_timer.c
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1 /*!**************************************************************************
2  @file stm32f103cb_timer.c
3  @brief Source file for stm32f103cb TIMER
4  @author Stuart Ianna
5  @version 0.1
6  @date June 2018
7  @copyright GNU GPLv3
8  @warning None
9  @bug
10 
11  @details
12 
13  @par Compilers
14  - arm-none-eabi-gcc (15:4.9.3+svn231177-1) 4.9.3 20150529 (prerelease)
15 ******************************************************************************/
16 #include "stm32f103cb_timer.h"
17 
18 typedef enum{
19 
20  T1C1_STAT = 0x1,
21  T1C2_STAT = 0x2,
22  T1C3_STAT = 0x4,
23  T1C4_STAT = 0x8,
24 
25  T2C1_STAT = 0x1,
26  T2C2_STAT = 0x2,
27  T2C3_STAT = 0x4,
28  T2C4_STAT = 0x8,
29 
30  T3C1_STAT = 0x1,
31  T3C2_STAT = 0x2,
32  T3C3_STAT = 0x4,
33  T3C4_STAT = 0x8,
34 
35  T4C1_STAT = 0x1,
36  T4C2_STAT = 0x2,
37  T4C3_STAT = 0x4,
38  T4C4_STAT = 0x8,
39 
40 }timer_capture;
41 
42 /****************************************************************************/
43 // TIMER1
44 /****************************************************************************/
45 
46 static mcu_error timer1_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty);
47 static mcu_error timer1_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse);
48 static mcu_error timer1_setupIC(timer_channel timerChannel);
49 
50 static void timer1_input_capture(void);
51 static void (*tim1_up_handler)(void);
52 static void (*tim1_cc_handler)(void);
53 
54 //This is all used with input capture
55 static volatile uint8_t t1_status;
56 static volatile uint16_t t1c1_rise;
57 static volatile uint16_t t1c2_rise;
58 static volatile uint16_t t1c3_rise;
59 static volatile uint16_t t1c4_rise;
60 static volatile uint16_t t1c1_cap;
61 static volatile uint16_t t1c2_cap;
62 static volatile uint16_t t1c3_cap;
63 static volatile uint16_t t1c4_cap;
64 
65 /****************************************************************************/
66 // TIMER2
67 /****************************************************************************/
68 
69 static mcu_error timer2_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty);
70 static mcu_error timer2_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse);
71 static mcu_error timer2_setupIC(timer_channel timerChannel);
72 
73 static void timer2_input_capture(void);
74 static void (*tim2_up_handler)(void);
75 
76 //This is all used with input capture
77 static volatile uint8_t t2_stat_reg;
78 static volatile uint8_t t2_status;
79 static volatile uint16_t t2c1_rise;
80 static volatile uint16_t t2c2_rise;
81 static volatile uint16_t t2c3_rise;
82 static volatile uint16_t t2c4_rise;
83 static volatile uint16_t t2c1_cap;
84 static volatile uint16_t t2c2_cap;
85 static volatile uint16_t t2c3_cap;
86 static volatile uint16_t t2c4_cap;
87 
88 /****************************************************************************/
89 // TIMER3
90 /****************************************************************************/
91 
92 static mcu_error timer3_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty);
93 static mcu_error timer3_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse);
94 static mcu_error timer3_setupIC(timer_channel timerChannel);
95 
96 static void timer3_input_capture(void);
97 static void (*tim3_up_handler)(void);
98 
99 //This is all used with input capture
100 static volatile uint8_t t3_status;
101 static volatile uint16_t t3c1_rise;
102 static volatile uint16_t t3c2_rise;
103 static volatile uint16_t t3c3_rise;
104 static volatile uint16_t t3c4_rise;
105 static volatile uint16_t t3c1_cap;
106 static volatile uint16_t t3c2_cap;
107 static volatile uint16_t t3c3_cap;
108 static volatile uint16_t t3c4_cap;
109 
110 /****************************************************************************/
111 // TIMER4
112 /****************************************************************************/
113 
114 static mcu_error timer4_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty);
115 static mcu_error timer4_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse);
116 static mcu_error timer4_setupIC(timer_channel timerChannel);
117 
118 static void timer4_input_capture(void);
119 static void (*tim4_up_handler)(void);
120 
121 //This is all used with input capture
122 static volatile uint8_t t4_status;
123 static volatile uint16_t t4c1_rise;
124 static volatile uint16_t t4c2_rise;
125 static volatile uint16_t t4c3_rise;
126 static volatile uint16_t t4c4_rise;
127 static volatile uint16_t t4c1_cap;
128 static volatile uint16_t t4c2_cap;
129 static volatile uint16_t t4c3_cap;
130 static volatile uint16_t t4c4_cap;
131 
132 /****************************************************************************/
133 // IRQ
134 /****************************************************************************/
135 
136 static void timer1_input_capture(void){
137 
138  if((TIM_SR(TIM1) & TIM_SR_UIF)){
139 
140  //This checks if a whole period has passed with no capture event for each channel
141  //Probably a better way to do this
142 
143  if(!(t1_status & T1C1_STAT)){
144 
145  t1c1_cap = 0;
146  }
147  if(!(t1_status & T1C2_STAT)){
148 
149  t1c2_cap = 0;
150  }
151  if(!(t1_status & T1C3_STAT)){
152 
153  t1c3_cap = 0;
154  }
155  if(!(t1_status & T1C4_STAT)){
156 
157  t1c4_cap = 0;
158  }
159 
160  t1_status = 0;
161  }
162 
163  if((TIM_SR(TIM1) & TIM_SR_CC1IF)){
164 
165  //Falling edge detection
166  if(TIM_CCER(TIM1) & TIM_CCER_CC1P){
167 
168  t1c1_cap = TIM_CCR1(TIM1) - t1c1_rise;
169 
170  //Set rising edge
171  TIM_CCER(TIM1) &= ~TIM_CCER_CC1P;
172 
173  //Mark read instance
174  t1_status |= T1C1_STAT;
175  }
176  //Rising edge detection
177  else{
178 
179  //Get rise time
180  t1c1_rise = TIM_CCR1(TIM1);
181 
182  //Set falling edge
183  TIM_CCER(TIM1) |= TIM_CCER_CC1P;
184 
185  //Mark read instance
186  t1_status |= T1C1_STAT;
187  }
188 
189  }
190  if((TIM_SR(TIM1) & TIM_SR_CC2IF)){
191 
192  //Falling edge detection
193  if(TIM_CCER(TIM1) & TIM_CCER_CC2P){
194 
195  //Record the time
196  t1c2_cap = TIM_CCR2(TIM1) - t1c2_rise;
197 
198  //Set rising edge
199  TIM_CCER(TIM1) &= ~TIM_CCER_CC2P;
200 
201  //Mark read instance
202  t1_status |= T1C2_STAT;
203  }
204  //Rising edge detection
205  else{
206 
207  t1c2_rise = TIM_CCR2(TIM1);
208 
209  //Set falling edge
210  TIM_CCER(TIM1) |= TIM_CCER_CC2P;
211 
212  //Mark read instance
213  t1_status |= T1C2_STAT;
214 
215  }
216  }
217  if((TIM_SR(TIM1) &TIM_SR_CC3IF)){
218 
219  //Falling edge detection
220  if(TIM_CCER(TIM1) & TIM_CCER_CC3P){
221 
222 
223  //Record the time
224  t1c3_cap = TIM_CCR3(TIM1) - t1c3_rise;
225 
226  //Set rising edge
227  TIM_CCER(TIM1) &= ~TIM_CCER_CC3P;
228 
229  //Mark read instance
230  t1_status |= T1C3_STAT;
231  }
232  //Rising edge detection
233  else{
234 
235  t1c3_rise = TIM_CCR3(TIM1);
236 
237  //Set falling edge
238  TIM_CCER(TIM1) |= TIM_CCER_CC3P;
239 
240  //Mark read instance
241  t1_status |= T1C3_STAT;
242 
243  }
244  }
245  if((TIM_SR(TIM1) & TIM_SR_CC4IF)){
246 
247  //Falling edge detection
248  if(TIM_CCER(TIM1) & TIM_CCER_CC4P){
249 
250  //Record the time
251  t1c4_cap = TIM_CCR4(TIM1) - t1c4_rise;
252 
253  //Set rising edge
254  TIM_CCER(TIM1) &= ~TIM_CCER_CC4P;
255 
256  //Mark read instance
257  t1_status |= T1C4_STAT;
258  }
259  //Rising edge detection
260  else{
261 
262  t1c4_rise = TIM_CCR4(TIM1);
263 
264  //Set falling edge
265  TIM_CCER(TIM1) |= TIM_CCER_CC4P;
266 
267  //Mark read instance
268  t1_status |= T1C4_STAT;
269 
270  }
271 
272  }
273 }
274 
275 static void timer2_input_capture(void){
276 
277  if(t2_stat_reg){
278 
279  //This checks if a whole period has passed with no capture event for each channel
280  //Probably a better way to do this
281 
282  if(!(t2_status & T2C1_STAT)){
283 
284  t2c1_cap = 0;
285  }
286  if(!(t2_status & T2C2_STAT)){
287 
288  t2c2_cap = 0;
289  }
290  if(!(t2_status & T2C3_STAT)){
291 
292  t1c3_cap = 0;
293  }
294  if(!(t2_status & T2C4_STAT)){
295 
296  t2c4_cap = 0;
297  }
298 
299  t2_status = 0;
300  }
301 
302  if((TIM_SR(TIM2) & TIM_SR_CC1IF)){
303 
304  //Falling edge detection
305  if(TIM_CCER(TIM2) & TIM_CCER_CC1P){
306 
307  t2c1_cap = TIM_CCR1(TIM2) - t2c1_rise;
308 
309  //Set rising edge
310  TIM_CCER(TIM2) &= ~TIM_CCER_CC1P;
311 
312  //Mark read instance
313  t2_status |= T2C1_STAT;
314  }
315  //Rising edge detection
316  else{
317 
318  //Get rise time
319  t2c1_rise = TIM_CCR1(TIM2);
320 
321  //Set falling edge
322  TIM_CCER(TIM2) |= TIM_CCER_CC1P;
323 
324  //Mark read instance
325  t2_status |= T2C1_STAT;
326  }
327 
328  }
329  if((TIM_SR(TIM2) & TIM_SR_CC2IF)){
330 
331  //Falling edge detection
332  if(TIM_CCER(TIM2) & TIM_CCER_CC2P){
333 
334 
335  //Record the time
336  t2c2_cap = TIM_CCR2(TIM2) - t2c2_rise;
337 
338  //Set rising edge
339  TIM_CCER(TIM2) &= ~TIM_CCER_CC2P;
340 
341  //Mark read instance
342  t2_status |= T2C2_STAT;
343  }
344  //Rising edge detection
345  else{
346 
347  t2c2_rise = TIM_CCR2(TIM2);
348 
349  //Set falling edge
350  TIM_CCER(TIM2) |= TIM_CCER_CC2P;
351 
352  //Mark read instance
353  t2_status |= T2C2_STAT;
354 
355  }
356  }
357  if((TIM_SR(TIM2) &TIM_SR_CC3IF)){
358 
359  //Falling edge detection
360  if(TIM_CCER(TIM2) & TIM_CCER_CC3P){
361 
362 
363  //Record the time
364  t2c3_cap = TIM_CCR3(TIM2) - t2c3_rise;
365 
366  //Set rising edge
367  TIM_CCER(TIM2) &= ~TIM_CCER_CC3P;
368 
369  //Mark read instance
370  t2_status |= T2C3_STAT;
371  }
372  //Rising edge detection
373  else{
374 
375  t2c3_rise = TIM_CCR3(TIM2);
376 
377  //Set falling edge
378  TIM_CCER(TIM2) |= TIM_CCER_CC3P;
379 
380  //Mark read instance
381  t2_status |= T2C3_STAT;
382 
383  }
384  }
385  if((TIM_SR(TIM2) & TIM_SR_CC4IF)){
386 
387  //Falling edge detection
388  if(TIM_CCER(TIM2) & TIM_CCER_CC4P){
389 
390  //Record the time
391  t2c4_cap = TIM_CCR4(TIM2) - t2c4_rise;
392 
393  //Set rising edge
394  TIM_CCER(TIM2) &= ~TIM_CCER_CC4P;
395 
396  //Mark read instance
397  t2_status |= T2C4_STAT;
398  }
399  //Rising edge detection
400  else{
401 
402  t2c4_rise = TIM_CCR4(TIM2);
403 
404  //Set falling edge
405  TIM_CCER(TIM2) |= TIM_CCER_CC4P;
406 
407  //Mark read instance
408  t2_status |= T2C4_STAT;
409 
410  }
411 
412  }
413 
414 }
415 
416 static void timer3_input_capture(void){
417 
418  if((TIM_SR(TIM3) & TIM_SR_UIF)){
419 
420  //This checks if a whole period has passed with no capture event for each channel
421  //Probably a better way to do this
422 
423  if(!(t3_status & T3C1_STAT)){
424 
425  t3c1_cap = 0;
426  }
427  if(!(t3_status & T3C2_STAT)){
428 
429  t3c2_cap = 0;
430  }
431  if(!(t3_status & T3C3_STAT)){
432 
433  t3c3_cap = 0;
434  }
435  if(!(t3_status & T3C4_STAT)){
436 
437  t3c4_cap = 0;
438  }
439 
440  t3_status = 0;
441  }
442 
443  if((TIM_SR(TIM3) & TIM_SR_CC1IF)){
444 
445  //Falling edge detection
446  if(TIM_CCER(TIM3) & TIM_CCER_CC1P){
447 
448  t3c1_cap = TIM_CCR1(TIM3) - t3c1_rise;
449 
450  //Set rising edge
451  TIM_CCER(TIM3) &= ~TIM_CCER_CC1P;
452 
453  //Mark read instance
454  t3_status |= T3C1_STAT;
455  }
456  //Rising edge detection
457  else{
458 
459  //Get rise time
460  t3c1_rise = TIM_CCR1(TIM3);
461 
462  //Set falling edge
463  TIM_CCER(TIM3) |= TIM_CCER_CC1P;
464 
465  //Mark read instance
466  t3_status |= T3C1_STAT;
467  }
468 
469  }
470  if((TIM_SR(TIM3) & TIM_SR_CC2IF)){
471 
472  //Falling edge detection
473  if(TIM_CCER(TIM3) & TIM_CCER_CC2P){
474 
475 
476  //Record the time
477  t3c2_cap = TIM_CCR2(TIM3) - t3c2_rise;
478 
479  //Set rising edge
480  TIM_CCER(TIM3) &= ~TIM_CCER_CC2P;
481 
482  //Mark read instance
483  t3_status |= T3C2_STAT;
484  }
485  //Rising edge detection
486  else{
487 
488  t3c2_rise = TIM_CCR2(TIM3);
489 
490  //Set falling edge
491  TIM_CCER(TIM3) |= TIM_CCER_CC2P;
492 
493  //Mark read instance
494  t3_status |= T3C2_STAT;
495 
496  }
497  }
498  if((TIM_SR(TIM3) &TIM_SR_CC3IF)){
499 
500  //Falling edge detection
501  if(TIM_CCER(TIM3) & TIM_CCER_CC3P){
502 
503 
504  //Record the time
505  t3c3_cap = TIM_CCR3(TIM3) - t3c3_rise;
506 
507  //Set rising edge
508  TIM_CCER(TIM3) &= ~TIM_CCER_CC3P;
509 
510  //Mark read instance
511  t3_status |= T2C3_STAT;
512  }
513  //Rising edge detection
514  else{
515 
516  t3c3_rise = TIM_CCR3(TIM3);
517 
518  //Set falling edge
519  TIM_CCER(TIM3) |= TIM_CCER_CC3P;
520 
521  //Mark read instance
522  t3_status |= T3C3_STAT;
523 
524  }
525  }
526  if((TIM_SR(TIM3) & TIM_SR_CC4IF)){
527 
528  //Falling edge detection
529  if(TIM_CCER(TIM3) & TIM_CCER_CC4P){
530 
531  //Record the time
532  t3c4_cap = TIM_CCR4(TIM3) - t3c4_rise;
533 
534  //Set rising edge
535  TIM_CCER(TIM3) &= ~TIM_CCER_CC4P;
536 
537  //Mark read instance
538  t3_status |= T3C4_STAT;
539  }
540  //Rising edge detection
541  else{
542 
543  t3c4_rise = TIM_CCR4(TIM3);
544 
545  //Set falling edge
546  TIM_CCER(TIM3) |= TIM_CCER_CC4P;
547 
548  //Mark read instance
549  t3_status |= T3C4_STAT;
550 
551  }
552 
553  }
554 }
555 
556 static void timer4_input_capture(void){
557 
558  if((TIM_SR(TIM4) & TIM_SR_UIF)){
559 
560  //This checks if a whole period has passed with no capture event for each channel
561  //Probably a better way to do this
562 
563  if(!(t4_status & T4C1_STAT)){
564 
565  t4c1_cap = 0;
566  }
567  if(!(t4_status & T4C2_STAT)){
568 
569  t4c2_cap = 0;
570  }
571  if(!(t4_status & T4C3_STAT)){
572 
573  t4c3_cap = 0;
574  }
575  if(!(t4_status & T4C4_STAT)){
576 
577  t4c4_cap = 0;
578  }
579 
580  t4_status = 0;
581  }
582 
583  if((TIM_SR(TIM4) & TIM_SR_CC1IF)){
584 
585  //Falling edge detection
586  if(TIM_CCER(TIM4) & TIM_CCER_CC1P){
587 
588  t4c1_cap = TIM_CCR1(TIM4) - t4c1_rise;
589 
590  //Set rising edge
591  TIM_CCER(TIM4) &= ~TIM_CCER_CC1P;
592 
593  //Mark read instance
594  t4_status |= T4C1_STAT;
595  }
596  //Rising edge detection
597  else{
598 
599  //Get rise time
600  t4c1_rise = TIM_CCR1(TIM4);
601 
602  //Set falling edge
603  TIM_CCER(TIM4) |= TIM_CCER_CC1P;
604 
605  //Mark read instance
606  t4_status |= T4C1_STAT;
607  }
608 
609  }
610  if((TIM_SR(TIM4) & TIM_SR_CC2IF)){
611 
612  //Falling edge detection
613  if(TIM_CCER(TIM4) & TIM_CCER_CC2P){
614 
615 
616  //Record the time
617  t4c2_cap = TIM_CCR2(TIM4) - t4c2_rise;
618 
619  //Set rising edge
620  TIM_CCER(TIM4) &= ~TIM_CCER_CC2P;
621 
622  //Mark read instance
623  t4_status |= T4C2_STAT;
624  }
625  //Rising edge detection
626  else{
627 
628  t4c2_rise = TIM_CCR2(TIM4);
629 
630  //Set falling edge
631  TIM_CCER(TIM4) |= TIM_CCER_CC2P;
632 
633  //Mark read instance
634  t4_status |= T4C2_STAT;
635 
636  }
637  }
638  if((TIM_SR(TIM4) &TIM_SR_CC3IF)){
639 
640  //Falling edge detection
641  if(TIM_CCER(TIM4) & TIM_CCER_CC3P){
642 
643 
644  //Record the time
645  t4c3_cap = TIM_CCR3(TIM4) - t4c3_rise;
646 
647  //Set rising edge
648  TIM_CCER(TIM4) &= ~TIM_CCER_CC3P;
649 
650  //Mark read instance
651  t4_status |= T2C3_STAT;
652  }
653  //Rising edge detection
654  else{
655 
656  t4c3_rise = TIM_CCR3(TIM4);
657 
658  //Set falling edge
659  TIM_CCER(TIM4) |= TIM_CCER_CC3P;
660 
661  //Mark read instance
662  t4_status |= T4C3_STAT;
663 
664  }
665  }
666  if((TIM_SR(TIM4) & TIM_SR_CC4IF)){
667 
668  //Falling edge detection
669  if(TIM_CCER(TIM4) & TIM_CCER_CC4P){
670 
671  //Record the time
672  t4c4_cap = TIM_CCR4(TIM4) - t4c4_rise;
673 
674  //Set rising edge
675  TIM_CCER(TIM4) &= ~TIM_CCER_CC4P;
676 
677  //Mark read instance
678  t4_status |= T4C4_STAT;
679  }
680  //Rising edge detection
681  else{
682 
683  t4c4_rise = TIM_CCR4(TIM4);
684 
685  //Set falling edge
686  TIM_CCER(TIM4) |= TIM_CCER_CC4P;
687 
688  //Mark read instance
689  t4_status |= T4C4_STAT;
690 
691  }
692 
693  }
694 }
695 
696 mcu_error TIMER_enableISR(timer_main timerNumber, void(*handler)(void)){
697 
698  mcu_error error;
699 
700  switch(timerNumber){
701 
702  case TIMER_1:
703 
704  nvic_disable_irq(NVIC_TIM1_UP_IRQ);
705  timer_disable_irq(TIM1,TIM_DIER_UIE);
706  tim1_up_handler = handler;
707  timer_enable_irq(TIM1,TIM_DIER_UIE);
708  nvic_enable_irq(NVIC_TIM1_UP_IRQ);
709  break;
710 
711  case TIMER_2:
712 
713  nvic_disable_irq(NVIC_TIM2_IRQ);
714  timer_disable_irq(TIM2,TIM_DIER_UIE);
715  tim2_up_handler = handler;
716  timer_enable_irq(TIM2,TIM_DIER_UIE);
717  nvic_enable_irq(NVIC_TIM2_IRQ);
718  break;
719 
720  case TIMER_3:
721 
722  nvic_disable_irq(NVIC_TIM3_IRQ);
723  timer_disable_irq(TIM3,TIM_DIER_UIE);
724  tim3_up_handler = handler;
725  timer_enable_irq(TIM3,TIM_DIER_UIE);
726  nvic_enable_irq(NVIC_TIM3_IRQ);
727  break;
728 
729  case TIMER_4:
730 
731  nvic_disable_irq(NVIC_TIM4_IRQ);
732  timer_disable_irq(TIM4,TIM_DIER_UIE);
733  tim4_up_handler = handler;
734  timer_enable_irq(TIM4,TIM_DIER_UIE);
735  nvic_enable_irq(NVIC_TIM4_IRQ);
736  break;
737 
738  default:
739  if(MCU_debugIsEnabled()){
740  MCU_printError(E_TIMER_NOTIMER);
741  }
742  error = E_TIMER_NOTIMER;
743 
744  break;
745  }
746 
747  return error;
748 
749 }
750 
751 mcu_error TIMER_disableISR(timer_main timerNumber){
752 
753  mcu_error error;
754 
755  switch(timerNumber){
756 
757  case TIMER_1:
758 
759  nvic_disable_irq(NVIC_TIM1_UP_IRQ);
760  timer_disable_irq(TIM1,TIM_DIER_UIE);
761 
762  break;
763  case TIMER_2:
764 
765  nvic_disable_irq(NVIC_TIM2_IRQ);
766  timer_disable_irq(TIM2,TIM_DIER_UIE);
767  break;
768  case TIMER_3:
769 
770  nvic_disable_irq(NVIC_TIM3_IRQ);
771  timer_disable_irq(TIM3,TIM_DIER_UIE);
772  break;
773  case TIMER_4:
774 
775  nvic_disable_irq(NVIC_TIM4_IRQ);
776  timer_disable_irq(TIM4,TIM_DIER_UIE);
777  break;
778  default:
779  if(MCU_debugIsEnabled()){
780  MCU_printError(E_TIMER_NOTIMER);
781  }
782  error = E_TIMER_NOTIMER;
783 
784  break;
785  }
786 
787  return error;
788 
789 }
790 
791 void tim1_cc_isr(void){
792 
793  tim1_cc_handler();
794  timer_clear_flag(TIM1,TIM_SR_UIF);
795 }
796 
797 void tim1_up_isr(void){
798 
799  tim1_up_handler();
800  timer_clear_flag(TIM1,TIM_SR_UIF);
801 }
802 
803 void tim2_isr(void){
804 
805  t2_stat_reg = TIM_SR(TIM2) & TIM_SR_UIF;
806  timer_clear_flag(TIM2,TIM_SR_UIF);
807  tim2_up_handler();
808 }
809 
810 void tim3_isr(void){
811 
812  timer_clear_flag(TIM3,TIM_SR_UIF);
813  tim3_up_handler();
814 }
815 
816 void tim4_isr(void){
817 
818  timer_clear_flag(TIM4,TIM_SR_UIF);
819  tim4_up_handler();
820 }
821 /****************************************************************************/
822 // PAUSE RESUME
823 /****************************************************************************/
824 
825 mcu_error TIMER_pause(timer_main timerNumber){
826 
827  mcu_error error = E_TIMER_NOERROR;
828 
829  switch(timerNumber){
830 
831  case TIMER_1:
832 
833  timer_disable_counter(TIM1);
834  break;
835  case TIMER_2:
836 
837  timer_disable_counter(TIM2);
838  break;
839  case TIMER_3:
840 
841  timer_disable_counter(TIM3);
842  break;
843  case TIMER_4:
844 
845  timer_disable_counter(TIM4);
846  break;
847  default:
848  if(MCU_debugIsEnabled()){
849  MCU_printError(E_TIMER_NOTIMER);
850  }
851  error = E_TIMER_NOTIMER;
852 
853  break;
854  }
855 
856  return error;
857 }
858 
859 mcu_error TIMER_resume(timer_main timerNumber){
860 
861  mcu_error error = E_TIMER_NOERROR;
862 
863  switch(timerNumber){
864 
865  case TIMER_1:
866 
867  timer_enable_counter(TIM1);
868  break;
869  case TIMER_2:
870 
871  timer_enable_counter(TIM2);
872  break;
873  case TIMER_3:
874 
875  timer_enable_counter(TIM3);
876  break;
877  case TIMER_4:
878 
879  timer_enable_counter(TIM4);
880  break;
881  default:
882  if(MCU_debugIsEnabled()){
883  MCU_printError(E_TIMER_NOTIMER);
884  }
885  error = E_TIMER_NOTIMER;
886 
887  break;
888  }
889 
890  return error;
891 }
892 
893 /****************************************************************************/
894 // SETUP FUNCTIONS
895 /****************************************************************************/
896 
897 mcu_error TIMER_setupIC(timer_main timerNumber, timer_channel timerChannel){
898 
899  mcu_error error = E_TIMER_NOERROR;
900 
901  switch(timerNumber){
902 
903  case TIMER_1:
904 
905  error = timer1_setupIC(timerChannel);
906  break;
907  case TIMER_2:
908 
909  error = timer2_setupIC(timerChannel);
910  TIMER_enableISR(TIMER_2,&timer2_input_capture);
911  break;
912  case TIMER_3:
913 
914  error = timer3_setupIC(timerChannel);
915  TIMER_enableISR(TIMER_3,&timer3_input_capture);
916  break;
917  case TIMER_4:
918 
919  error = timer4_setupIC(timerChannel);
920  TIMER_enableISR(TIMER_4,&timer4_input_capture);
921  break;
922  default:
923  if(MCU_debugIsEnabled()){
924  MCU_printError(E_TIMER_NOTIMER);
925  }
926  error = E_TIMER_NOTIMER;
927 
928  break;
929  }
930 
931  return error;
932 }
933 
934 mcu_error TIMER_setupPWM(timer_main timerNumber, timer_channel timerChannel, uint32_t frequency, uint8_t duty){
935 
936  mcu_error error = E_TIMER_NOERROR;
937 
938  switch(timerNumber){
939 
940  case TIMER_1:
941 
942  error = timer1_setupPWM(timerChannel,frequency,duty);
943  break;
944  case TIMER_2:
945 
946  error = timer2_setupPWM(timerChannel,frequency,duty);
947  break;
948  case TIMER_3:
949 
950  error = timer3_setupPWM(timerChannel,frequency,duty);
951  break;
952  case TIMER_4:
953 
954  error = timer4_setupPWM(timerChannel,frequency,duty);
955  break;
956  default:
957  if(MCU_debugIsEnabled()){
958  MCU_printError(E_TIMER_NOTIMER);
959  }
960  error = E_TIMER_NOTIMER;
961 
962  break;
963  }
964 
965  return error;
966 }
967 mcu_error TIMER_setupPulse(timer_main timerNumber, timer_channel timerChannel, uint32_t frequency, uint32_t pulse){
968 
969  mcu_error error = E_TIMER_NOERROR;
970 
971  switch(timerNumber){
972 
973  case TIMER_1:
974 
975  error = timer1_setupPulse(timerChannel,frequency,pulse);
976  break;
977  case TIMER_2:
978 
979  error = timer2_setupPulse(timerChannel,frequency,pulse);
980  break;
981  case TIMER_3:
982 
983  error = timer3_setupPulse(timerChannel,frequency,pulse);
984  break;
985  case TIMER_4:
986 
987  error = timer4_setupPulse(timerChannel,frequency,pulse);
988  break;
989  default:
990  if(MCU_debugIsEnabled()){
991  MCU_printError(E_TIMER_NOTIMER);
992  }
993  error = E_TIMER_NOTIMER;
994 
995  break;
996  }
997 
998  return error;
999 }
1000 
1001 mcu_error TIMER_setupCount(timer_main timerNumber, uint32_t frequency, void (*handler)(void)){
1002 
1003  mcu_error error = E_TIMER_NOERROR;
1004 
1005  switch(timerNumber){
1006 
1007  case TIMER_1:
1008 
1009  //Set the clock
1010  rcc_periph_clock_enable(RCC_TIM1);
1011 
1012  //Setup main timer
1013  timer_disable_counter(TIM1);
1014  timer_reset(TIM1);
1015  timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1016  TIMER_setFrequency(TIMER_1,frequency);
1017 
1018  TIMER_enableISR(timerNumber,handler);
1019 
1020  timer_enable_counter(TIM1);
1021 
1022  break;
1023  case TIMER_2:
1024 
1025  //Set the clock
1026  rcc_periph_clock_enable(RCC_TIM2);
1027 
1028  //Setup main timer
1029  timer_disable_counter(TIM2);
1030  timer_reset(TIM2);
1031  timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1032  TIMER_setFrequency(timerNumber ,frequency);
1033 
1034  TIMER_enableISR(timerNumber,handler);
1035 
1036  timer_enable_counter(TIM2);
1037 
1038  break;
1039  case TIMER_3:
1040 
1041  //Set the clock
1042  rcc_periph_clock_enable(RCC_TIM3);
1043 
1044  //Setup main timer
1045  timer_disable_counter(TIM3);
1046  timer_reset(TIM3);
1047  timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1048  TIMER_setFrequency(timerNumber, frequency);
1049 
1050  TIMER_enableISR(timerNumber,handler);
1051 
1052  timer_enable_counter(TIM3);
1053  break;
1054 
1055  case TIMER_4:
1056 
1057  //Set the clock
1058  rcc_periph_clock_enable(RCC_TIM4);
1059 
1060  //Setup main timer
1061  timer_disable_counter(TIM4);
1062  timer_reset(TIM4);
1063  timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1064  TIMER_setFrequency(timerNumber, frequency);
1065 
1066  TIMER_enableISR(timerNumber,handler);
1067 
1068  timer_enable_counter(TIM4);
1069  break;
1070 
1071  default:
1072  if(MCU_debugIsEnabled()){
1073  MCU_printError(E_TIMER_NOTIMER);
1074  }
1075  error = E_TIMER_NOTIMER;
1076 
1077  break;
1078  }
1079 
1080  return error;
1081 
1082 
1083 }
1084 
1085 static mcu_error timer1_setupIC(timer_channel timerChannel){
1086 
1087  mcu_error error;
1088 
1089  //Set the clock
1090  rcc_periph_clock_enable(RCC_TIM1);
1091 
1092  //Setup main timer
1093  timer_disable_counter(TIM1);
1094  timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1095  TIMER_setPeriod(TIMER_1,0xFFFF);
1096 
1097  switch(timerChannel){
1098 
1099  case CHANNEL_1:
1100 
1101  pinSetup(GPIO_IC,PORTA,PIN8);
1102 
1103  TIM_CCMR1(TIM1) |= TIM_CCMR1_CC1S_IN_TI1;
1104  TIM_CCER(TIM1) |= TIM_CCER_CC1E;
1105 
1106  //Set inital trigger as rising
1107  TIM_CCER(TIM1) &= ~TIM_CCER_CC1P;
1108 
1109  //Interrupts have different configuration for advanced timers
1110  nvic_disable_irq(NVIC_TIM1_CC_IRQ);
1111  timer_enable_irq(TIM1,TIM_DIER_CC1IE);
1112  tim1_cc_handler = timer1_input_capture;
1113  nvic_enable_irq(NVIC_TIM1_CC_IRQ);
1114 
1115  timer_enable_counter(TIM1);
1116  break;
1117 
1118  case CHANNEL_2:
1119 
1120  pinSetup(GPIO_IC,PORTA,PIN9);
1121 
1122  TIM_CCMR1(TIM1) |= TIM_CCMR1_CC2S_IN_TI2;
1123  TIM_CCER(TIM1) |= TIM_CCER_CC2E;
1124 
1125  //Set inital trigger as rising
1126  TIM_CCER(TIM1) &= ~TIM_CCER_CC2P;
1127 
1128  //Interrupts have different configuration for advanced timers
1129  nvic_disable_irq(NVIC_TIM1_CC_IRQ);
1130  timer_enable_irq(TIM1,TIM_DIER_CC2IE);
1131  tim1_cc_handler = timer1_input_capture;
1132  nvic_enable_irq(NVIC_TIM1_CC_IRQ);
1133 
1134  timer_enable_counter(TIM1);
1135  break;
1136 
1137  case CHANNEL_3:
1138 
1139  pinSetup(GPIO_IC,PORTA,PIN10);
1140 
1141  TIM_CCMR2(TIM1) |= TIM_CCMR2_CC3S_IN_TI3;
1142  TIM_CCER(TIM1) |= TIM_CCER_CC3E;
1143 
1144  //Set inital trigger as rising
1145  TIM_CCER(TIM1) &= ~TIM_CCER_CC3P;
1146 
1147  //Interrupts have different configuration for advanced timers
1148  nvic_disable_irq(NVIC_TIM1_CC_IRQ);
1149  timer_enable_irq(TIM1,TIM_DIER_CC3IE);
1150  tim1_cc_handler = timer1_input_capture;
1151  nvic_enable_irq(NVIC_TIM1_CC_IRQ);
1152 
1153  timer_enable_counter(TIM1);
1154 
1155  break;
1156  case CHANNEL_4:
1157 
1158  pinSetup(GPIO_IC,PORTA,PIN11);
1159 
1160  TIM_CCMR2(TIM1) |= TIM_CCMR2_CC4S_IN_TI4;
1161  TIM_CCER(TIM1) |= TIM_CCER_CC4E;
1162 
1163  //Set inital trigger as rising
1164  TIM_CCER(TIM1) &= ~TIM_CCER_CC4P;
1165 
1166  //Interrupts have different configuration for advanced timers
1167  nvic_disable_irq(NVIC_TIM1_CC_IRQ);
1168  timer_enable_irq(TIM1,TIM_DIER_CC4IE);
1169  tim1_cc_handler = timer1_input_capture;
1170  nvic_enable_irq(NVIC_TIM1_CC_IRQ);
1171 
1172  timer_enable_counter(TIM1);
1173  break;
1174 
1175  default:
1176  if(MCU_debugIsEnabled()){
1177  MCU_printError(E_TIMER_NOCHANNEL);
1178  }
1179  error = E_TIMER_NOCHANNEL;
1180  break;
1181  }
1182 
1183  return error;
1184 }
1185 
1186 static mcu_error timer2_setupIC(timer_channel timerChannel){
1187 
1188  mcu_error error;
1189 
1190  //Set the clock
1191  rcc_periph_clock_enable(RCC_TIM2);
1192 
1193  //Setup main timer
1194  timer_disable_counter(TIM2);
1195  timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1196  TIMER_setPeriod(TIMER_2,0xFFFF);
1197 
1198  switch(timerChannel){
1199 
1200  case CHANNEL_1:
1201 
1202  pinSetup(GPIO_IC,PORTA,PIN0);
1203 
1204  TIM_CCMR1(TIM2) |= TIM_CCMR1_CC1S_IN_TI1;
1205  TIM_CCER(TIM2) |= TIM_CCER_CC1E;
1206 
1207  //Set inital trigger as rising
1208  TIM_CCER(TIM2) &= ~TIM_CCER_CC1P;
1209 
1210  timer_enable_irq(TIM2,TIM_DIER_CC1IE);
1211 
1212  timer_enable_counter(TIM2);
1213  break;
1214 
1215  case CHANNEL_2:
1216 
1217  pinSetup(GPIO_IC,PORTA,PIN1);
1218 
1219  TIM_CCMR1(TIM2) |= TIM_CCMR1_CC2S_IN_TI2;
1220  TIM_CCER(TIM2) |= TIM_CCER_CC2E;
1221 
1222  //Set inital trigger as rising
1223  TIM_CCER(TIM2) &= ~TIM_CCER_CC2P;
1224 
1225  timer_enable_irq(TIM2,TIM_DIER_CC2IE);
1226 
1227  timer_enable_counter(TIM2);
1228  break;
1229 
1230  case CHANNEL_3:
1231 
1232  pinSetup(GPIO_IC,PORTA,PIN2);
1233 
1234  TIM_CCMR2(TIM2) |= TIM_CCMR2_CC3S_IN_TI3;
1235  TIM_CCER(TIM2) |= TIM_CCER_CC3E;
1236 
1237  //Set inital trigger as rising
1238  TIM_CCER(TIM2) &= ~TIM_CCER_CC3P;
1239 
1240  timer_enable_irq(TIM2,TIM_DIER_CC3IE);
1241 
1242  timer_enable_counter(TIM2);
1243 
1244  break;
1245  case CHANNEL_4:
1246 
1247  pinSetup(GPIO_IC,PORTA,PIN3);
1248 
1249  TIM_CCMR2(TIM2) |= TIM_CCMR2_CC4S_IN_TI4;
1250  TIM_CCER(TIM2) |= TIM_CCER_CC4E;
1251 
1252  //Set inital trigger as rising
1253  TIM_CCER(TIM2) &= ~TIM_CCER_CC4P;
1254 
1255  timer_enable_irq(TIM2,TIM_DIER_CC4IE);
1256 
1257  timer_enable_counter(TIM2);
1258  break;
1259 
1260  default:
1261  if(MCU_debugIsEnabled()){
1262  MCU_printError(E_TIMER_NOCHANNEL);
1263  }
1264  error = E_TIMER_NOCHANNEL;
1265  break;
1266  }
1267 
1268  return error;
1269 }
1270 
1271 static mcu_error timer3_setupIC(timer_channel timerChannel){
1272 
1273  mcu_error error;
1274 
1275  //Set the clock
1276  rcc_periph_clock_enable(RCC_TIM3);
1277 
1278  //Setup main timer
1279  timer_disable_counter(TIM3);
1280  timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1281  TIMER_setPeriod(TIMER_3,0xFFFF);
1282 
1283  switch(timerChannel){
1284 
1285  case CHANNEL_1:
1286 
1287  pinSetup(GPIO_IC,PORTA,PIN6);
1288 
1289  TIM_CCMR1(TIM3) |= TIM_CCMR1_CC1S_IN_TI1;
1290  TIM_CCER(TIM3) |= TIM_CCER_CC1E;
1291 
1292  //Set inital trigger as rising
1293  TIM_CCER(TIM3) &= ~TIM_CCER_CC1P;
1294 
1295  timer_enable_irq(TIM3,TIM_DIER_CC1IE);
1296 
1297  timer_enable_counter(TIM3);
1298  break;
1299 
1300  case CHANNEL_2:
1301 
1302  pinSetup(GPIO_IC,PORTA,PIN7);
1303 
1304  TIM_CCMR1(TIM3) |= TIM_CCMR1_CC2S_IN_TI2;
1305  TIM_CCER(TIM3) |= TIM_CCER_CC2E;
1306 
1307  //Set inital trigger as rising
1308  TIM_CCER(TIM3) &= ~TIM_CCER_CC2P;
1309 
1310  timer_enable_irq(TIM3,TIM_DIER_CC2IE);
1311 
1312  timer_enable_counter(TIM3);
1313  break;
1314 
1315  case CHANNEL_3:
1316 
1317  pinSetup(GPIO_IC,PORTB,PIN0);
1318 
1319  TIM_CCMR2(TIM3) |= TIM_CCMR2_CC3S_IN_TI3;
1320  TIM_CCER(TIM3) |= TIM_CCER_CC3E;
1321 
1322  //Set inital trigger as rising
1323  TIM_CCER(TIM3) &= ~TIM_CCER_CC3P;
1324 
1325  timer_enable_irq(TIM3,TIM_DIER_CC3IE);
1326 
1327  timer_enable_counter(TIM3);
1328 
1329  break;
1330  case CHANNEL_4:
1331 
1332  pinSetup(GPIO_IC,PORTB,PIN1);
1333 
1334  TIM_CCMR2(TIM3) |= TIM_CCMR2_CC4S_IN_TI4;
1335  TIM_CCER(TIM3) |= TIM_CCER_CC4E;
1336 
1337  //Set inital trigger as rising
1338  TIM_CCER(TIM3) &= ~TIM_CCER_CC4P;
1339 
1340  timer_enable_irq(TIM3,TIM_DIER_CC4IE);
1341 
1342  timer_enable_counter(TIM3);
1343  break;
1344 
1345  default:
1346  if(MCU_debugIsEnabled()){
1347  MCU_printError(E_TIMER_NOCHANNEL);
1348  }
1349  error = E_TIMER_NOCHANNEL;
1350  break;
1351  }
1352 
1353  return error;
1354 }
1355 
1356 static mcu_error timer4_setupIC(timer_channel timerChannel){
1357 
1358  mcu_error error;
1359 
1360  //Set the clock
1361  rcc_periph_clock_enable(RCC_TIM4);
1362 
1363  //Setup main timer
1364  timer_disable_counter(TIM4);
1365  timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_UP);
1366  TIMER_setPeriod(TIMER_4,0xFFFF);
1367 
1368  switch(timerChannel){
1369 
1370  case CHANNEL_1:
1371 
1372  pinSetup(GPIO_IC,PORTB,PIN6);
1373 
1374  TIM_CCMR1(TIM4) |= TIM_CCMR1_CC1S_IN_TI1;
1375  TIM_CCER(TIM4) |= TIM_CCER_CC1E;
1376 
1377  //Set inital trigger as rising
1378  TIM_CCER(TIM4) &= ~TIM_CCER_CC1P;
1379 
1380  timer_enable_irq(TIM4,TIM_DIER_CC1IE);
1381 
1382  timer_enable_counter(TIM4);
1383  break;
1384 
1385  case CHANNEL_2:
1386 
1387  pinSetup(GPIO_IC,PORTB,PIN7);
1388 
1389  TIM_CCMR1(TIM4) |= TIM_CCMR1_CC2S_IN_TI2;
1390  TIM_CCER(TIM4) |= TIM_CCER_CC2E;
1391 
1392  //Set inital trigger as rising
1393  TIM_CCER(TIM4) &= ~TIM_CCER_CC2P;
1394 
1395  timer_enable_irq(TIM4,TIM_DIER_CC2IE);
1396 
1397  timer_enable_counter(TIM4);
1398  break;
1399 
1400  case CHANNEL_3:
1401 
1402  pinSetup(GPIO_IC,PORTB,PIN8);
1403 
1404  TIM_CCMR2(TIM4) |= TIM_CCMR2_CC3S_IN_TI3;
1405  TIM_CCER(TIM4) |= TIM_CCER_CC3E;
1406 
1407  //Set inital trigger as rising
1408  TIM_CCER(TIM4) &= ~TIM_CCER_CC3P;
1409 
1410  timer_enable_irq(TIM4,TIM_DIER_CC3IE);
1411 
1412  timer_enable_counter(TIM4);
1413 
1414  break;
1415  case CHANNEL_4:
1416 
1417  pinSetup(GPIO_IC,PORTB,PIN9);
1418 
1419  TIM_CCMR2(TIM4) |= TIM_CCMR2_CC4S_IN_TI4;
1420  TIM_CCER(TIM4) |= TIM_CCER_CC4E;
1421 
1422  //Set inital trigger as rising
1423  TIM_CCER(TIM4) &= ~TIM_CCER_CC4P;
1424 
1425  timer_enable_irq(TIM4,TIM_DIER_CC4IE);
1426 
1427  timer_enable_counter(TIM4);
1428  break;
1429 
1430  default:
1431  if(MCU_debugIsEnabled()){
1432  MCU_printError(E_TIMER_NOCHANNEL);
1433  }
1434  error = E_TIMER_NOCHANNEL;
1435  break;
1436  }
1437 
1438  return error;
1439 
1440 }
1441 
1442 uint16_t TIMER_getIC(timer_main timerNumber, timer_channel channel){
1443 
1444  switch(timerNumber){
1445 
1446  case TIMER_1:
1447 
1448  switch(channel){
1449 
1450  case CHANNEL_1:
1451 
1452  return t1c1_cap;
1453  break;
1454 
1455  case CHANNEL_2:
1456 
1457  return t1c2_cap;
1458  break;
1459 
1460  case CHANNEL_3:
1461 
1462  return t1c3_cap;
1463  break;
1464 
1465  case CHANNEL_4:
1466 
1467  return t1c4_cap;
1468  break;
1469  }
1470 
1471  break;
1472  case TIMER_2:
1473 
1474  switch(channel){
1475 
1476  case CHANNEL_1:
1477 
1478  return t2c1_cap;
1479  break;
1480 
1481  case CHANNEL_2:
1482 
1483  return t2c2_cap;
1484  break;
1485 
1486  case CHANNEL_3:
1487 
1488  return t2c3_cap;
1489  break;
1490 
1491  case CHANNEL_4:
1492 
1493  return t2c4_cap;
1494  break;
1495  }
1496  break;
1497  case TIMER_3:
1498 
1499  switch(channel){
1500 
1501  case CHANNEL_1:
1502 
1503  return t3c1_cap;
1504  break;
1505 
1506  case CHANNEL_2:
1507 
1508  return t3c2_cap;
1509  break;
1510 
1511  case CHANNEL_3:
1512 
1513  return t3c3_cap;
1514  break;
1515 
1516  case CHANNEL_4:
1517 
1518  return t3c4_cap;
1519  break;
1520  }
1521 
1522  break;
1523  case TIMER_4:
1524 
1525  switch(channel){
1526 
1527  case CHANNEL_1:
1528 
1529  return t4c1_cap;
1530  break;
1531 
1532  case CHANNEL_2:
1533 
1534  return t4c2_cap;
1535  break;
1536 
1537  case CHANNEL_3:
1538 
1539  return t4c3_cap;
1540  break;
1541 
1542  case CHANNEL_4:
1543 
1544  return t4c4_cap;
1545  break;
1546  }
1547  break;
1548 
1549  default:
1550  if(MCU_debugIsEnabled()){
1551  MCU_printError(E_TIMER_NOTIMER);
1552  }
1553  return E_TIMER_NOTIMER;
1554 
1555  break;
1556  }
1557 
1558  return E_TIMER_NOERROR;
1559 
1560 
1561 }
1562 
1563 mcu_error timer1_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty){
1564 
1565  mcu_error error;
1566 
1567  //Set the clock
1568  rcc_periph_clock_enable(RCC_TIM1);
1569 
1570  //Setup main timer
1571  timer_disable_counter(TIM1);
1572  timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1573  timer_enable_break_main_output(TIM1);
1574 
1575  switch(timerChannel){
1576 
1577  case CHANNEL_1:
1578 
1579  pinSetup(GPIO_PWM,PORTA,PIN8);
1580 
1581  timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
1582  timer_enable_oc_output(TIM1, TIM_OC1);
1583  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1584  TIMER_setDuty(TIMER_1,CHANNEL_1,duty);
1585  timer_enable_counter(TIM1);
1586  break;
1587 
1588  case CHANNEL_2:
1589 
1590  pinSetup(GPIO_PWM,PORTA,PIN9);
1591 
1592  timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
1593  timer_enable_oc_output(TIM1, TIM_OC2);
1594  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1595  TIMER_setDuty(TIMER_1,CHANNEL_2,duty);
1596  timer_enable_counter(TIM1);
1597  break;
1598  case CHANNEL_3:
1599 
1600  pinSetup(GPIO_PWM,PORTA,PIN10);
1601 
1602  timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
1603  timer_enable_oc_output(TIM1, TIM_OC3);
1604  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1605  TIMER_setDuty(TIMER_1,CHANNEL_3,duty);
1606  timer_enable_counter(TIM1);
1607  break;
1608  case CHANNEL_4:
1609 
1610  pinSetup(GPIO_PWM,PORTA,PIN11);
1611 
1612  timer_set_oc_mode(TIM1, TIM_OC4, TIM_OCM_PWM1);
1613  timer_enable_oc_output(TIM1, TIM_OC4);
1614  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1615  TIMER_setDuty(TIMER_1,CHANNEL_4,duty);
1616  timer_enable_counter(TIM1);
1617  break;
1618 
1619  default:
1620  if(MCU_debugIsEnabled()){
1621  MCU_printError(E_TIMER_NOCHANNEL);
1622  }
1623  error = E_TIMER_NOCHANNEL;
1624  break;
1625  }
1626 
1627  return error;
1628 
1629 }
1630 
1631 
1632 mcu_error timer2_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty){
1633 
1634  mcu_error error;
1635 
1636  //Set the clock
1637  rcc_periph_clock_enable(RCC_TIM2);
1638 
1639  //Setup main timer
1640  timer_disable_counter(TIM2);
1641  timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1642 
1643  switch(timerChannel){
1644 
1645  case CHANNEL_1:
1646 
1647  pinSetup(GPIO_PWM,PORTA,PIN0);
1648 
1649  timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_PWM1);
1650  timer_enable_oc_output(TIM2, TIM_OC1);
1651  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1652  TIMER_setDuty(TIMER_2,CHANNEL_1,duty);
1653  timer_enable_counter(TIM2);
1654  break;
1655 
1656  case CHANNEL_2:
1657 
1658  pinSetup(GPIO_PWM,PORTA,PIN1);
1659 
1660  timer_set_oc_mode(TIM2, TIM_OC2, TIM_OCM_PWM1);
1661  timer_enable_oc_output(TIM2, TIM_OC2);
1662  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1663  TIMER_setDuty(TIMER_2,CHANNEL_2,duty);
1664  timer_enable_counter(TIM2);
1665  break;
1666 
1667  case CHANNEL_3:
1668 
1669  pinSetup(GPIO_PWM,PORTA,PIN2);
1670 
1671  timer_set_oc_mode(TIM2, TIM_OC3, TIM_OCM_PWM1);
1672  timer_enable_oc_output(TIM2, TIM_OC3);
1673  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1674  TIMER_setDuty(TIMER_2,CHANNEL_3,duty);
1675  timer_enable_counter(TIM2);
1676  break;
1677  case CHANNEL_4:
1678 
1679  pinSetup(GPIO_PWM,PORTA,PIN3);
1680 
1681  timer_set_oc_mode(TIM2, TIM_OC4, TIM_OCM_PWM1);
1682  timer_enable_oc_output(TIM2, TIM_OC4);
1683  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1684  TIMER_setDuty(TIMER_2,CHANNEL_4,duty);
1685  timer_enable_counter(TIM2);
1686  break;
1687 
1688  default:
1689  if(MCU_debugIsEnabled()){
1690  MCU_printError(E_TIMER_NOCHANNEL);
1691  }
1692  error = E_TIMER_NOCHANNEL;
1693  break;
1694  }
1695 
1696  return error;
1697 }
1698 
1699 mcu_error timer3_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty){
1700 
1701  mcu_error error;
1702 
1703  //Set the clock
1704  rcc_periph_clock_enable(RCC_TIM3);
1705 
1706  //Setup main timer
1707  timer_disable_counter(TIM3);
1708  timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1709 
1710  switch(timerChannel){
1711 
1712  case CHANNEL_1:
1713 
1714  pinSetup(GPIO_PWM,PORTA,PIN6);
1715 
1716  timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1);
1717  timer_enable_oc_output(TIM3, TIM_OC1);
1718  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
1719  TIMER_setDuty(TIMER_3,CHANNEL_1,duty);
1720  timer_enable_counter(TIM3);
1721  break;
1722 
1723  case CHANNEL_2:
1724 
1725  pinSetup(GPIO_PWM,PORTA,PIN7);
1726 
1727  timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
1728  timer_enable_oc_output(TIM3, TIM_OC2);
1729  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
1730  TIMER_setDuty(TIMER_3,CHANNEL_2,duty);
1731  timer_enable_counter(TIM3);
1732  break;
1733 
1734  case CHANNEL_3:
1735 
1736  pinSetup(GPIO_PWM,PORTB,PIN0);
1737 
1738  timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
1739  timer_enable_oc_output(TIM3, TIM_OC3);
1740  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
1741  TIMER_setDuty(TIMER_3,CHANNEL_3,duty);
1742  timer_enable_counter(TIM3);
1743  break;
1744 
1745  case CHANNEL_4:
1746 
1747  pinSetup(GPIO_PWM,PORTB,PIN1);
1748 
1749  timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
1750  timer_enable_oc_output(TIM3, TIM_OC4);
1751  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
1752  TIMER_setDuty(TIMER_3,CHANNEL_4,duty);
1753  timer_enable_counter(TIM3);
1754  break;
1755 
1756  default:
1757  if(MCU_debugIsEnabled()){
1758  MCU_printError(E_TIMER_NOCHANNEL);
1759  }
1760  error = E_TIMER_NOCHANNEL;
1761  break;
1762  }
1763 
1764  return error;
1765 
1766 }
1767 
1768 mcu_error timer4_setupPWM(timer_channel timerChannel, uint32_t frequency, uint8_t duty){
1769 
1770  mcu_error error;
1771 
1772  //Set the clock
1773  rcc_periph_clock_enable(RCC_TIM4);
1774 
1775  //Setup main timer
1776  timer_disable_counter(TIM4);
1777  timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1778 
1779  switch(timerChannel){
1780 
1781  case CHANNEL_1:
1782 
1783  pinSetup(GPIO_PWM,PORTB,PIN6);
1784 
1785  timer_set_oc_mode(TIM4, TIM_OC1, TIM_OCM_PWM1);
1786  timer_enable_oc_output(TIM4, TIM_OC1);
1787  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
1788  TIMER_setDuty(TIMER_4,CHANNEL_1,duty);
1789  timer_enable_counter(TIM4);
1790  break;
1791 
1792  case CHANNEL_2:
1793 
1794  pinSetup(GPIO_PWM,PORTB,PIN7);
1795 
1796  timer_set_oc_mode(TIM4, TIM_OC2, TIM_OCM_PWM1);
1797  timer_enable_oc_output(TIM4, TIM_OC2);
1798  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
1799  TIMER_setDuty(TIMER_4,CHANNEL_2,duty);
1800  timer_enable_counter(TIM4);
1801  break;
1802 
1803  case CHANNEL_3:
1804 
1805  pinSetup(GPIO_PWM,PORTB,PIN8);
1806 
1807  timer_set_oc_mode(TIM4, TIM_OC3, TIM_OCM_PWM1);
1808  timer_enable_oc_output(TIM4, TIM_OC3);
1809  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
1810  TIMER_setDuty(TIMER_4,CHANNEL_3,duty);
1811  timer_enable_counter(TIM4);
1812  break;
1813 
1814  case CHANNEL_4:
1815 
1816  pinSetup(GPIO_PWM,PORTB,PIN9);
1817 
1818  timer_set_oc_mode(TIM4, TIM_OC4, TIM_OCM_PWM1);
1819  timer_enable_oc_output(TIM4, TIM_OC4);
1820  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
1821  TIMER_setDuty(TIMER_4,CHANNEL_4,duty);
1822  timer_enable_counter(TIM4);
1823  break;
1824 
1825  default:
1826  if(MCU_debugIsEnabled()){
1827  MCU_printError(E_TIMER_NOCHANNEL);
1828  }
1829  error = E_TIMER_NOCHANNEL;
1830  break;
1831  }
1832 
1833  return error;
1834 
1835 }
1836 
1837 mcu_error timer1_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse){
1838 
1839  mcu_error error;
1840 
1841  //Set the clock
1842  rcc_periph_clock_enable(RCC_TIM1);
1843 
1844  //Setup main timer
1845  timer_disable_counter(TIM1);
1846  timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1847  timer_enable_break_main_output(TIM1);
1848 
1849  switch(timerChannel){
1850 
1851  case CHANNEL_1:
1852 
1853  pinSetup(GPIO_PWM,PORTA,PIN8);
1854 
1855  timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
1856  timer_enable_oc_output(TIM1, TIM_OC1);
1857  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1858  TIMER_setPulse(TIMER_1,CHANNEL_1,pulse);
1859  timer_enable_counter(TIM1);
1860  break;
1861 
1862  case CHANNEL_2:
1863 
1864  pinSetup(GPIO_PWM,PORTA,PIN9);
1865 
1866  timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
1867  timer_enable_oc_output(TIM1, TIM_OC2);
1868  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1869  TIMER_setPulse(TIMER_1,CHANNEL_2,pulse);
1870  timer_enable_counter(TIM1);
1871  break;
1872  case CHANNEL_3:
1873 
1874  pinSetup(GPIO_PWM,PORTA,PIN10);
1875 
1876  timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
1877  timer_enable_oc_output(TIM1, TIM_OC3);
1878  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1879  TIMER_setPulse(TIMER_1,CHANNEL_3,pulse);
1880  timer_enable_counter(TIM1);
1881 
1882  break;
1883  case CHANNEL_4:
1884 
1885  pinSetup(GPIO_PWM,PORTA,PIN11);
1886 
1887  timer_set_oc_mode(TIM1, TIM_OC4, TIM_OCM_PWM1);
1888  timer_enable_oc_output(TIM1, TIM_OC4);
1889  TIMER_setPeriod(TIMER_1,(uint32_t)(1000000.0f/(float)frequency));
1890  TIMER_setPulse(TIMER_1,CHANNEL_4,pulse);
1891  timer_enable_counter(TIM1);
1892  break;
1893 
1894  default:
1895  if(MCU_debugIsEnabled()){
1896  MCU_printError(E_TIMER_NOCHANNEL);
1897  }
1898  error = E_TIMER_NOCHANNEL;
1899  break;
1900  }
1901 
1902  return error;
1903 }
1904 
1905 mcu_error timer2_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse){
1906 
1907  mcu_error error;
1908 
1909  //Set the clock
1910  rcc_periph_clock_enable(RCC_TIM2);
1911 
1912  //Setup main timer
1913  timer_disable_counter(TIM2);
1914  timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1915 
1916  switch(timerChannel){
1917 
1918  case CHANNEL_1:
1919 
1920  pinSetup(GPIO_PWM,PORTA,PIN0);
1921 
1922  timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_PWM1);
1923  timer_enable_oc_output(TIM2, TIM_OC1);
1924  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1925  TIMER_setPulse(TIMER_2,CHANNEL_1,pulse);
1926  timer_enable_counter(TIM2);
1927  break;
1928 
1929  case CHANNEL_2:
1930 
1931  pinSetup(GPIO_PWM,PORTA,PIN1);
1932 
1933  timer_set_oc_mode(TIM2, TIM_OC2, TIM_OCM_PWM1);
1934  timer_enable_oc_output(TIM2, TIM_OC2);
1935  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1936  TIMER_setPulse(TIMER_2,CHANNEL_2,pulse);
1937  timer_enable_counter(TIM2);
1938  break;
1939 
1940  case CHANNEL_3:
1941 
1942  pinSetup(GPIO_PWM,PORTA,PIN2);
1943 
1944  timer_set_oc_mode(TIM2, TIM_OC3, TIM_OCM_PWM1);
1945  timer_enable_oc_output(TIM2, TIM_OC3);
1946  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1947  TIMER_setPulse(TIMER_2,CHANNEL_3,pulse);
1948  timer_enable_counter(TIM2);
1949 
1950  break;
1951 
1952  case CHANNEL_4:
1953 
1954  pinSetup(GPIO_PWM,PORTA,PIN3);
1955 
1956  timer_set_oc_mode(TIM2, TIM_OC4, TIM_OCM_PWM1);
1957  timer_enable_oc_output(TIM2, TIM_OC4);
1958  TIMER_setPeriod(TIMER_2,(uint32_t)(1000000.0f/(float)frequency));
1959  TIMER_setPulse(TIMER_2,CHANNEL_4,pulse);
1960  timer_enable_counter(TIM2);
1961  break;
1962 
1963  default:
1964  if(MCU_debugIsEnabled()){
1965  MCU_printError(E_TIMER_NOCHANNEL);
1966  }
1967  error = E_TIMER_NOCHANNEL;
1968  break;
1969  }
1970 
1971  return error;
1972 
1973 }
1974 
1975 mcu_error timer3_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse){
1976 
1977  mcu_error error;
1978 
1979  //Set the clock
1980  rcc_periph_clock_enable(RCC_TIM3);
1981 
1982  //Setup main timer
1983  timer_disable_counter(TIM3);
1984  timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
1985 
1986  switch(timerChannel){
1987 
1988  case CHANNEL_1:
1989 
1990  pinSetup(GPIO_PWM,PORTA,PIN6);
1991 
1992  timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1);
1993  timer_enable_oc_output(TIM3, TIM_OC1);
1994  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
1995  TIMER_setPulse(TIMER_3,CHANNEL_1,pulse);
1996  timer_enable_counter(TIM3);
1997  break;
1998 
1999  case CHANNEL_2:
2000 
2001  pinSetup(GPIO_PWM,PORTA,PIN7);
2002 
2003  timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
2004  timer_enable_oc_output(TIM3, TIM_OC2);
2005  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
2006  TIMER_setPulse(TIMER_3,CHANNEL_2,pulse);
2007  timer_enable_counter(TIM3);
2008  break;
2009 
2010  case CHANNEL_3:
2011 
2012  pinSetup(GPIO_PWM,PORTB,PIN0);
2013 
2014  timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
2015  timer_enable_oc_output(TIM3, TIM_OC3);
2016  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
2017  TIMER_setPulse(TIMER_3,CHANNEL_3,pulse);
2018  timer_enable_counter(TIM3);
2019 
2020  break;
2021 
2022  case CHANNEL_4:
2023 
2024  pinSetup(GPIO_PWM,PORTB,PIN1);
2025 
2026  timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
2027  timer_enable_oc_output(TIM3, TIM_OC4);
2028  TIMER_setPeriod(TIMER_3,(uint32_t)(1000000.0f/(float)frequency));
2029  TIMER_setPulse(TIMER_3,CHANNEL_4,pulse);
2030  timer_enable_counter(TIM3);
2031  break;
2032 
2033  default:
2034  if(MCU_debugIsEnabled()){
2035  MCU_printError(E_TIMER_NOCHANNEL);
2036  }
2037  error = E_TIMER_NOCHANNEL;
2038  break;
2039  }
2040 
2041  return error;
2042 
2043 }
2044 
2045 mcu_error timer4_setupPulse(timer_channel timerChannel,uint32_t frequency,uint32_t pulse){
2046 
2047  mcu_error error;
2048 
2049  //Set the clock
2050  rcc_periph_clock_enable(RCC_TIM4);
2051 
2052  //Setup main timer
2053  timer_disable_counter(TIM4);
2054  timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,TIM_CR1_DIR_DOWN);
2055 
2056  switch(timerChannel){
2057 
2058  case CHANNEL_1:
2059 
2060  pinSetup(GPIO_PWM,PORTB,PIN6);
2061 
2062  timer_set_oc_mode(TIM4, TIM_OC1, TIM_OCM_PWM1);
2063  timer_enable_oc_output(TIM4, TIM_OC1);
2064  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
2065  TIMER_setPulse(TIMER_4,CHANNEL_1,pulse);
2066  timer_enable_counter(TIM4);
2067  break;
2068 
2069  case CHANNEL_2:
2070 
2071  pinSetup(GPIO_PWM,PORTB,PIN7);
2072 
2073  timer_set_oc_mode(TIM4, TIM_OC2, TIM_OCM_PWM1);
2074  timer_enable_oc_output(TIM4, TIM_OC2);
2075  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
2076  TIMER_setPulse(TIMER_4,CHANNEL_2,pulse);
2077  timer_enable_counter(TIM4);
2078  break;
2079 
2080  case CHANNEL_3:
2081 
2082  pinSetup(GPIO_PWM,PORTB,PIN8);
2083 
2084  timer_set_oc_mode(TIM4, TIM_OC3, TIM_OCM_PWM1);
2085  timer_enable_oc_output(TIM4, TIM_OC3);
2086  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
2087  TIMER_setPulse(TIMER_4,CHANNEL_3,pulse);
2088  timer_enable_counter(TIM4);
2089 
2090  break;
2091 
2092  case CHANNEL_4:
2093 
2094  pinSetup(GPIO_PWM,PORTB,PIN9);
2095 
2096  timer_set_oc_mode(TIM4, TIM_OC4, TIM_OCM_PWM1);
2097  timer_enable_oc_output(TIM4, TIM_OC4);
2098  TIMER_setPeriod(TIMER_4,(uint32_t)(1000000.0f/(float)frequency));
2099  TIMER_setPulse(TIMER_4,CHANNEL_4,pulse);
2100  timer_enable_counter(TIM4);
2101  break;
2102 
2103  default:
2104  if(MCU_debugIsEnabled()){
2105  MCU_printError(E_TIMER_NOCHANNEL);
2106  }
2107  error = E_TIMER_NOCHANNEL;
2108  break;
2109  }
2110 
2111  return error;
2112 
2113 
2114 }
2115 /****************************************************************************/
2116 // GET / SET COUNT
2117 /****************************************************************************/
2118 
2119 uint16_t TIMER_getCount(timer_main timerNumber){
2120 
2121  switch(timerNumber){
2122 
2123  case TIMER_1:
2124 
2125  return TIM_CNT(TIM1);
2126  break;
2127  case TIMER_2:
2128 
2129  return TIM_CNT(TIM2);
2130  break;
2131 
2132  case TIMER_3:
2133 
2134  return TIM_CNT(TIM3);
2135  break;
2136 
2137  case TIMER_4:
2138 
2139  return TIM_CNT(TIM4);
2140  break;
2141 
2142  default:
2143  if(MCU_debugIsEnabled()){
2144  MCU_printError(E_TIMER_NOTIMER);
2145  }
2146  return E_TIMER_NOTIMER;
2147 
2148  break;
2149  }
2150 
2151  return E_TIMER_NOERROR;
2152 
2153 }
2154 mcu_error TIMER_setCount(timer_main timerNumber, uint16_t count){
2155 
2156  switch(timerNumber){
2157 
2158  case TIMER_1:
2159 
2160  TIM_CNT(TIM1) = count;
2161  break;
2162  case TIMER_2:
2163 
2164  TIM_CNT(TIM2) = count;
2165  break;
2166 
2167  case TIMER_3:
2168 
2169  TIM_CNT(TIM3) = count;
2170  break;
2171 
2172  case TIMER_4:
2173 
2174  TIM_CNT(TIM4) = count;
2175  break;
2176 
2177  default:
2178  if(MCU_debugIsEnabled()){
2179  MCU_printError(E_TIMER_NOTIMER);
2180  }
2181  return E_TIMER_NOTIMER;
2182 
2183  break;
2184  }
2185 
2186  return E_TIMER_NOERROR;
2187 
2188 
2189 }
2190 /****************************************************************************/
2191 // PERIOD / FREQUENCY
2192 /****************************************************************************/
2193 mcu_error TIMER_setPeriod(timer_main timerNumber, uint32_t period){
2194 
2195  uint32_t prescaler;
2196 
2197  switch(timerNumber){
2198 
2199  case TIMER_1:
2200 
2201  //Timer 1 runs on apb2, so at full clock speed, get the clock cycles per microsecond
2202  prescaler = (CLOCK_getSpeed()/1000000);
2203 
2204  if(period <= 0xFFFF){
2205 
2206  timer_set_prescaler(TIM1,prescaler-1);
2207  timer_set_period(TIM1, period-1);
2208 
2209  }
2210  else if(period <= 655350){
2211 
2212  prescaler *= 10;
2213  timer_set_prescaler(TIM1,prescaler-1);
2214  timer_set_period(TIM1, (period/10.0) - 1);
2215  }
2216  else if(period <= 6553500){
2217 
2218  prescaler *= 100;
2219  timer_set_prescaler(TIM1,prescaler-1);
2220  timer_set_period(TIM1, (period/100.0) -1);
2221  }
2222  else{
2223 
2224  //Too long
2225  if(MCU_debugIsEnabled()){
2226  MCU_printError(E_TIMER_PERIOD);
2227  }
2228  return E_TIMER_PERIOD;
2229  }
2230 
2231  break;
2232 
2233  case TIMER_2:
2234 
2235  //Timer 2 runs on apb1, get the clock cycles per microsecond
2236  prescaler = (CLOCK_getSpeed()/1000000);
2237 
2238  if(period <= 0xFFFF){
2239 
2240  timer_set_prescaler(TIM2,prescaler-1);
2241  timer_set_period(TIM2, period-1);
2242 
2243  }
2244  else if(period < 655350){
2245 
2246  prescaler *= 10;
2247  timer_set_prescaler(TIM2,prescaler-1);
2248  timer_set_period(TIM2, (period/10.0) - 1);
2249  }
2250  else if(period < 6553500){
2251 
2252  prescaler *= 100;
2253  timer_set_prescaler(TIM2,prescaler-1);
2254  timer_set_period(TIM2, (period/100.0) -1);
2255  }
2256  else{
2257 
2258  //Too long
2259  if(MCU_debugIsEnabled()){
2260  MCU_printError(E_TIMER_PERIOD);
2261  }
2262  return E_TIMER_PERIOD;
2263  }
2264  break;
2265 
2266  case TIMER_3:
2267 
2268  //Timer 2 runs on apb1, get the clock cycles per microsecond
2269  prescaler = (CLOCK_getSpeed()/1000000);
2270 
2271  if(period <= 0xFFFF){
2272 
2273  timer_set_prescaler(TIM3,prescaler-1);
2274  timer_set_period(TIM3, period-1);
2275 
2276  }
2277  else if(period < 655350){
2278 
2279  prescaler *= 10;
2280  timer_set_prescaler(TIM3,prescaler-1);
2281  timer_set_period(TIM3, (period/10.0) - 1);
2282  }
2283  else if(period < 6553500){
2284 
2285  prescaler *= 100;
2286  timer_set_prescaler(TIM3,prescaler-1);
2287  timer_set_period(TIM3, (period/100.0) -1);
2288  }
2289  else{
2290 
2291  //Too long
2292  if(MCU_debugIsEnabled()){
2293  MCU_printError(E_TIMER_PERIOD);
2294  }
2295  return E_TIMER_PERIOD;
2296  }
2297  break;
2298 
2299  case TIMER_4:
2300 
2301  prescaler = (CLOCK_getSpeed()/1000000);
2302 
2303  if(period <= 0xFFFF){
2304 
2305  timer_set_prescaler(TIM4,prescaler-1);
2306  timer_set_period(TIM4, period-1);
2307 
2308  }
2309  else if(period < 655350){
2310 
2311  prescaler *= 10;
2312  timer_set_prescaler(TIM4,prescaler-1);
2313  timer_set_period(TIM4, (period/10.0) - 1);
2314  }
2315  else if(period < 6553500){
2316 
2317  prescaler *= 100;
2318  timer_set_prescaler(TIM4,prescaler-1);
2319  timer_set_period(TIM4, (period/100.0) -1);
2320  }
2321  else{
2322 
2323  //Too long
2324  if(MCU_debugIsEnabled()){
2325  MCU_printError(E_TIMER_PERIOD);
2326  }
2327  return E_TIMER_PERIOD;
2328  }
2329  break;
2330 
2331  default:
2332  if(MCU_debugIsEnabled()){
2333  MCU_printError(E_TIMER_NOTIMER);
2334  }
2335  return E_TIMER_NOTIMER;
2336 
2337  break;
2338  }
2339 
2340  return E_TIMER_NOERROR;
2341 
2342 }
2343 
2344 mcu_error TIMER_setFrequency(timer_main timerNumber, uint32_t frequency){
2345 
2346  mcu_error error = E_TIMER_NOERROR;
2347  switch(timerNumber){
2348 
2349  case TIMER_1:
2350 
2351  error = TIMER_setPeriod(timerNumber,1000000.0f/(float)frequency);
2352  break;
2353 
2354  case TIMER_2:
2355 
2356  error = TIMER_setPeriod(timerNumber,1000000.0f/(float)frequency);
2357  break;
2358 
2359  case TIMER_3:
2360 
2361  error = TIMER_setPeriod(timerNumber,1000000.0f/(float)frequency);
2362  break;
2363 
2364  case TIMER_4:
2365 
2366  error = TIMER_setPeriod(timerNumber,1000000.0f/(float)frequency);
2367  break;
2368 
2369  default:
2370  if(MCU_debugIsEnabled()){
2371  MCU_printError(E_TIMER_NOTIMER);
2372  }
2373  error = E_TIMER_NOTIMER;
2374 
2375  break;
2376  }
2377 
2378  return error;
2379 
2380 }
2381 
2382 mcu_error TIMER_setDuty(timer_main timerNumber, timer_channel channel, uint8_t duty){
2383 
2384  if (duty > 100){
2385 
2386  duty = 100;
2387  }
2388 
2389 
2390  switch(timerNumber){
2391 
2392  case TIMER_1:
2393 
2394  switch(channel){
2395 
2396  case CHANNEL_1:
2397 
2398  //Timer doesn't completely disable with 0 duty cycle
2399  if(duty == 0){
2400 
2401  TIM_CCER(TIM1) &= ~TIM_CCER_CC1E;
2402  }
2403  else{
2404  TIM_CCER(TIM1) |= TIM_CCER_CC1E;
2405  timer_set_oc_value(TIM1, TIM_OC1, TIM_ARR(TIM1)*((float)(duty)/100.0f));
2406 
2407  }
2408 
2409  break;
2410 
2411  case CHANNEL_2:
2412 
2413  //Timer doesn't completely disable with 0 duty cycle
2414  if(duty == 0){
2415 
2416  TIM_CCER(TIM1) &= ~TIM_CCER_CC2E;
2417  }
2418  else{
2419  TIM_CCER(TIM1) |= TIM_CCER_CC2E;
2420  timer_set_oc_value(TIM1, TIM_OC2, TIM_ARR(TIM1)*((float)(duty)/100.0f));
2421 
2422  }
2423  break;
2424 
2425  case CHANNEL_3:
2426 
2427  //Timer doesn't completely disable with 0 duty cycle
2428  if(duty == 0){
2429 
2430  TIM_CCER(TIM1) &= ~TIM_CCER_CC3E;
2431  }
2432  else{
2433  TIM_CCER(TIM1) |= TIM_CCER_CC3E;
2434  timer_set_oc_value(TIM1, TIM_OC3, TIM_ARR(TIM1)*((float)(duty)/100.0f));
2435 
2436  }
2437  break;
2438 
2439  case CHANNEL_4:
2440 
2441  //Timer doesn't completely disable with 0 duty cycle
2442  if(duty == 0){
2443 
2444  TIM_CCER(TIM1) &= ~TIM_CCER_CC4E;
2445  }
2446  else{
2447  TIM_CCER(TIM1) |= TIM_CCER_CC4E;
2448  timer_set_oc_value(TIM1, TIM_OC4, TIM_ARR(TIM1)*((float)(duty)/100.0f));
2449 
2450  }
2451  break;
2452  }
2453 
2454  break;
2455  case TIMER_2:
2456 
2457  switch(channel){
2458 
2459  case CHANNEL_1:
2460 
2461  //Timer doesn't completely disable with 0 duty cycle
2462  if(duty == 0){
2463 
2464  TIM_CCER(TIM2) &= ~TIM_CCER_CC1E;
2465  }
2466  else{
2467  TIM_CCER(TIM2) |= TIM_CCER_CC1E;
2468  timer_set_oc_value(TIM2, TIM_OC1, TIM_ARR(TIM2)*((float)(duty)/100.0f));
2469 
2470  }
2471 
2472  break;
2473 
2474  case CHANNEL_2:
2475 
2476  //Timer doesn't completely disable with 0 duty cycle
2477  if(duty == 0){
2478 
2479  TIM_CCER(TIM2) &= ~TIM_CCER_CC2E;
2480  }
2481  else{
2482  TIM_CCER(TIM2) |= TIM_CCER_CC2E;
2483  timer_set_oc_value(TIM2, TIM_OC2, TIM_ARR(TIM2)*((float)(duty)/100.0f));
2484 
2485  }
2486  break;
2487 
2488  case CHANNEL_3:
2489 
2490  //Timer doesn't completely disable with 0 duty cycle
2491  if(duty == 0){
2492 
2493  TIM_CCER(TIM2) &= ~TIM_CCER_CC3E;
2494  }
2495  else{
2496  TIM_CCER(TIM2) |= TIM_CCER_CC3E;
2497  timer_set_oc_value(TIM2, TIM_OC3, TIM_ARR(TIM2)*((float)(duty)/100.0f));
2498 
2499  }
2500  break;
2501 
2502  case CHANNEL_4:
2503 
2504  //Timer doesn't completely disable with 0 duty cycle
2505  if(duty == 0){
2506 
2507  TIM_CCER(TIM2) &= ~TIM_CCER_CC4E;
2508  }
2509  else{
2510  TIM_CCER(TIM2) |= TIM_CCER_CC4E;
2511  timer_set_oc_value(TIM2, TIM_OC4, TIM_ARR(TIM2)*((float)(duty)/100.0f));
2512 
2513  }
2514  break;
2515  }
2516  break;
2517  case TIMER_3:
2518 
2519  switch(channel){
2520 
2521  case CHANNEL_1:
2522 
2523  //Timer doesn't completely disable with 0 duty cycle
2524  if(duty == 0){
2525 
2526  TIM_CCER(TIM3) &= ~TIM_CCER_CC1E;
2527  }
2528  else{
2529  TIM_CCER(TIM3) |= TIM_CCER_CC1E;
2530  timer_set_oc_value(TIM3, TIM_OC1, TIM_ARR(TIM3)*((float)(duty)/100.0f));
2531 
2532  }
2533 
2534  break;
2535 
2536  case CHANNEL_2:
2537 
2538  //Timer doesn't completely disable with 0 duty cycle
2539  if(duty == 0){
2540 
2541  TIM_CCER(TIM3) &= ~TIM_CCER_CC2E;
2542  }
2543  else{
2544  TIM_CCER(TIM3) |= TIM_CCER_CC2E;
2545  timer_set_oc_value(TIM3, TIM_OC2, TIM_ARR(TIM3)*((float)(duty)/100.0f));
2546 
2547  }
2548  break;
2549 
2550  case CHANNEL_3:
2551 
2552  //Timer doesn't completely disable with 0 duty cycle
2553  if(duty == 0){
2554 
2555  TIM_CCER(TIM3) &= ~TIM_CCER_CC3E;
2556  }
2557  else{
2558  TIM_CCER(TIM3) |= TIM_CCER_CC3E;
2559  timer_set_oc_value(TIM3, TIM_OC3, TIM_ARR(TIM3)*((float)(duty)/100.0f));
2560 
2561  }
2562  break;
2563 
2564  case CHANNEL_4:
2565 
2566  //Timer doesn't completely disable with 0 duty cycle
2567  if(duty == 0){
2568 
2569  TIM_CCER(TIM3) &= ~TIM_CCER_CC4E;
2570  }
2571  else{
2572  TIM_CCER(TIM3) |= TIM_CCER_CC4E;
2573  timer_set_oc_value(TIM3, TIM_OC4, TIM_ARR(TIM3)*((float)(duty)/100.0f));
2574 
2575  }
2576  break;
2577  }
2578  break;
2579  case TIMER_4:
2580 
2581  switch(channel){
2582 
2583  case CHANNEL_1:
2584 
2585  //Timer doesn't completely disable with 0 duty cycle
2586  if(duty == 0){
2587 
2588  TIM_CCER(TIM4) &= ~TIM_CCER_CC1E;
2589  }
2590  else{
2591  TIM_CCER(TIM4) |= TIM_CCER_CC1E;
2592  timer_set_oc_value(TIM4, TIM_OC1, TIM_ARR(TIM4)*((float)(duty)/100.0f));
2593 
2594  }
2595 
2596  break;
2597 
2598  case CHANNEL_2:
2599 
2600  //Timer doesn't completely disable with 0 duty cycle
2601  if(duty == 0){
2602 
2603  TIM_CCER(TIM4) &= ~TIM_CCER_CC2E;
2604  }
2605  else{
2606  TIM_CCER(TIM4) |= TIM_CCER_CC2E;
2607  timer_set_oc_value(TIM4, TIM_OC2, TIM_ARR(TIM4)*((float)(duty)/100.0f));
2608 
2609  }
2610  break;
2611 
2612  case CHANNEL_3:
2613 
2614  //Timer doesn't completely disable with 0 duty cycle
2615  if(duty == 0){
2616 
2617  TIM_CCER(TIM4) &= ~TIM_CCER_CC3E;
2618  }
2619  else{
2620  TIM_CCER(TIM4) |= TIM_CCER_CC3E;
2621  timer_set_oc_value(TIM4, TIM_OC3, TIM_ARR(TIM4)*((float)(duty)/100.0f));
2622 
2623  }
2624  break;
2625 
2626  case CHANNEL_4:
2627 
2628  //Timer doesn't completely disable with 0 duty cycle
2629  if(duty == 0){
2630 
2631  TIM_CCER(TIM4) &= ~TIM_CCER_CC4E;
2632  }
2633  else{
2634  TIM_CCER(TIM4) |= TIM_CCER_CC4E;
2635  timer_set_oc_value(TIM4, TIM_OC4, TIM_ARR(TIM4)*((float)(duty)/100.0f));
2636 
2637  }
2638  break;
2639  }
2640  break;
2641  default:
2642  if(MCU_debugIsEnabled()){
2643  MCU_printError(E_TIMER_NOTIMER);
2644  }
2645  return E_TIMER_NOTIMER;
2646 
2647  break;
2648  }
2649 
2650  return E_TIMER_NOERROR;
2651 
2652 }
2653 mcu_error TIMER_setPulse(timer_main timerNumber, timer_channel channel, uint32_t pulse){
2654 
2655  mcu_error error = E_TIMER_NOERROR;
2656 
2657  switch(timerNumber){
2658 
2659  case TIMER_1:
2660 
2661  switch(channel){
2662 
2663  case CHANNEL_1:
2664 
2665  //Timer doesn't turn off completely at 0
2666  if(pulse == 0){
2667 
2668  TIM_CCER(TIM1) &= ~TIM_CCER_CC1E;
2669 
2670  }
2671  else{
2672 
2673  if(pulse > TIM_ARR(TIM1)){
2674 
2675  error = E_TIMER_PULSE;
2676  pulse = TIM_ARR(TIM1);
2677 
2678  if(MCU_debugIsEnabled()){
2679  MCU_printError(E_TIMER_PULSE);
2680  }
2681 
2682  }
2683  TIM_CCER(TIM1) |= TIM_CCER_CC1E;
2684  timer_set_oc_value(TIM1, TIM_OC1, pulse-1);
2685  }
2686 
2687  break;
2688 
2689  case CHANNEL_2:
2690 
2691  //Timer doesn't turn off completely at 0
2692  if(pulse == 0){
2693 
2694  TIM_CCER(TIM1) &= ~TIM_CCER_CC2E;
2695 
2696  }
2697  else{
2698 
2699  if(pulse > TIM_ARR(TIM1)){
2700 
2701  error = E_TIMER_PULSE;
2702  pulse = TIM_ARR(TIM1);
2703 
2704  if(MCU_debugIsEnabled()){
2705  MCU_printError(E_TIMER_PULSE);
2706  }
2707 
2708  }
2709  TIM_CCER(TIM1) |= TIM_CCER_CC2E;
2710  timer_set_oc_value(TIM1, TIM_OC2, pulse-1);
2711  }
2712  break;
2713 
2714  case CHANNEL_3:
2715  //Timer doesn't turn off completely at 0
2716  if(pulse == 0){
2717 
2718  TIM_CCER(TIM1) &= ~TIM_CCER_CC3E;
2719 
2720  }
2721  else{
2722 
2723  if(pulse > TIM_ARR(TIM1)){
2724 
2725  error = E_TIMER_PULSE;
2726  pulse = TIM_ARR(TIM1);
2727 
2728  if(MCU_debugIsEnabled()){
2729  MCU_printError(E_TIMER_PULSE);
2730  }
2731 
2732  }
2733  TIM_CCER(TIM1) |= TIM_CCER_CC3E;
2734  timer_set_oc_value(TIM1, TIM_OC3, pulse-1);
2735  }
2736  break;
2737 
2738  case CHANNEL_4:
2739 
2740  //Timer doesn't turn off completely at 0
2741  if(pulse == 0){
2742 
2743  TIM_CCER(TIM1) &= ~TIM_CCER_CC4E;
2744 
2745  }
2746  else{
2747 
2748  if(pulse > TIM_ARR(TIM1)){
2749 
2750  error = E_TIMER_PULSE;
2751  pulse = TIM_ARR(TIM1);
2752 
2753  if(MCU_debugIsEnabled()){
2754  MCU_printError(E_TIMER_PULSE);
2755  }
2756 
2757  }
2758  TIM_CCER(TIM1) |= TIM_CCER_CC4E;
2759  timer_set_oc_value(TIM1, TIM_OC4, pulse-1);
2760  }
2761  break;
2762  }
2763 
2764  break;
2765  case TIMER_2:
2766 
2767  switch(channel){
2768 
2769  case CHANNEL_1:
2770 
2771  //Timer doesn't turn off completely at 0
2772  if(pulse == 0){
2773 
2774  TIM_CCER(TIM2) &= ~TIM_CCER_CC1E;
2775 
2776  }
2777  else{
2778 
2779  if(pulse > TIM_ARR(TIM2)){
2780 
2781  error = E_TIMER_PULSE;
2782  pulse = TIM_ARR(TIM2);
2783 
2784  if(MCU_debugIsEnabled()){
2785  MCU_printError(E_TIMER_PULSE);
2786  }
2787 
2788  }
2789  TIM_CCER(TIM2) |= TIM_CCER_CC1E;
2790  timer_set_oc_value(TIM2, TIM_OC1, pulse-1);
2791  }
2792 
2793  break;
2794 
2795  case CHANNEL_2:
2796 
2797  //Timer doesn't turn off completely at 0
2798  if(pulse == 0){
2799 
2800  TIM_CCER(TIM2) &= ~TIM_CCER_CC2E;
2801 
2802  }
2803  else{
2804 
2805  if(pulse > TIM_ARR(TIM2)){
2806 
2807  error = E_TIMER_PULSE;
2808  pulse = TIM_ARR(TIM2);
2809 
2810  if(MCU_debugIsEnabled()){
2811  MCU_printError(E_TIMER_PULSE);
2812  }
2813 
2814  }
2815  TIM_CCER(TIM2) |= TIM_CCER_CC2E;
2816  timer_set_oc_value(TIM2, TIM_OC2, pulse-1);
2817  }
2818  break;
2819 
2820  case CHANNEL_3:
2821  //Timer doesn't turn off completely at 0
2822  if(pulse == 0){
2823 
2824  TIM_CCER(TIM2) &= ~TIM_CCER_CC3E;
2825 
2826  }
2827  else{
2828 
2829  if(pulse > TIM_ARR(TIM2)){
2830 
2831  error = E_TIMER_PULSE;
2832  pulse = TIM_ARR(TIM2);
2833 
2834  if(MCU_debugIsEnabled()){
2835  MCU_printError(E_TIMER_PULSE);
2836  }
2837 
2838  }
2839  TIM_CCER(TIM2) |= TIM_CCER_CC3E;
2840  timer_set_oc_value(TIM2, TIM_OC3, pulse-1);
2841  }
2842  break;
2843 
2844  case CHANNEL_4:
2845 
2846  //Timer doesn't turn off completely at 0
2847  if(pulse == 0){
2848 
2849  TIM_CCER(TIM2) &= ~TIM_CCER_CC4E;
2850 
2851  }
2852  else{
2853 
2854  if(pulse > TIM_ARR(TIM2)){
2855 
2856  error = E_TIMER_PULSE;
2857  pulse = TIM_ARR(TIM2);
2858 
2859  if(MCU_debugIsEnabled()){
2860  MCU_printError(E_TIMER_PULSE);
2861  }
2862 
2863  }
2864  TIM_CCER(TIM2) |= TIM_CCER_CC4E;
2865  timer_set_oc_value(TIM2, TIM_OC4, pulse-1);
2866  }
2867  break;
2868  }
2869 
2870  break;
2871  case TIMER_3:
2872 
2873  switch(channel){
2874 
2875  case CHANNEL_1:
2876 
2877  //Timer doesn't turn off completely at 0
2878  if(pulse == 0){
2879 
2880  TIM_CCER(TIM3) &= ~TIM_CCER_CC1E;
2881 
2882  }
2883  else{
2884 
2885  if(pulse > TIM_ARR(TIM3)){
2886 
2887  error = E_TIMER_PULSE;
2888  pulse = TIM_ARR(TIM3);
2889 
2890  if(MCU_debugIsEnabled()){
2891  MCU_printError(E_TIMER_PULSE);
2892  }
2893 
2894  }
2895  TIM_CCER(TIM3) |= TIM_CCER_CC1E;
2896  timer_set_oc_value(TIM3, TIM_OC1, pulse-1);
2897  }
2898 
2899  break;
2900 
2901  case CHANNEL_2:
2902 
2903  //Timer doesn't turn off completely at 0
2904  if(pulse == 0){
2905 
2906  TIM_CCER(TIM3) &= ~TIM_CCER_CC2E;
2907 
2908  }
2909  else{
2910 
2911  if(pulse > TIM_ARR(TIM3)){
2912 
2913  error = E_TIMER_PULSE;
2914  pulse = TIM_ARR(TIM3);
2915 
2916  if(MCU_debugIsEnabled()){
2917  MCU_printError(E_TIMER_PULSE);
2918  }
2919 
2920  }
2921  TIM_CCER(TIM3) |= TIM_CCER_CC2E;
2922  timer_set_oc_value(TIM3, TIM_OC2, pulse-1);
2923  }
2924  break;
2925 
2926  case CHANNEL_3:
2927  //Timer doesn't turn off completely at 0
2928  if(pulse == 0){
2929 
2930  TIM_CCER(TIM3) &= ~TIM_CCER_CC3E;
2931 
2932  }
2933  else{
2934 
2935  if(pulse > TIM_ARR(TIM3)){
2936 
2937  error = E_TIMER_PULSE;
2938  pulse = TIM_ARR(TIM3);
2939 
2940  if(MCU_debugIsEnabled()){
2941  MCU_printError(E_TIMER_PULSE);
2942  }
2943 
2944  }
2945  TIM_CCER(TIM3) |= TIM_CCER_CC3E;
2946  timer_set_oc_value(TIM3, TIM_OC3, pulse-1);
2947  }
2948  break;
2949 
2950  case CHANNEL_4:
2951 
2952  //Timer doesn't turn off completely at 0
2953  if(pulse == 0){
2954 
2955  TIM_CCER(TIM3) &= ~TIM_CCER_CC4E;
2956 
2957  }
2958  else{
2959 
2960  if(pulse > TIM_ARR(TIM3)){
2961 
2962  error = E_TIMER_PULSE;
2963  pulse = TIM_ARR(TIM3);
2964 
2965  if(MCU_debugIsEnabled()){
2966  MCU_printError(E_TIMER_PULSE);
2967  }
2968 
2969  }
2970  TIM_CCER(TIM3) |= TIM_CCER_CC4E;
2971  timer_set_oc_value(TIM3, TIM_OC4, pulse-1);
2972  }
2973  break;
2974  }
2975 
2976  break;
2977  case TIMER_4:
2978 
2979  switch(channel){
2980 
2981  case CHANNEL_1:
2982 
2983  //Timer doesn't turn off completely at 0
2984  if(pulse == 0){
2985 
2986  TIM_CCER(TIM4) &= ~TIM_CCER_CC1E;
2987 
2988  }
2989  else{
2990 
2991  if(pulse > TIM_ARR(TIM4)){
2992 
2993  error = E_TIMER_PULSE;
2994  pulse = TIM_ARR(TIM4);
2995 
2996  if(MCU_debugIsEnabled()){
2997  MCU_printError(E_TIMER_PULSE);
2998  }
2999 
3000  }
3001  TIM_CCER(TIM4) |= TIM_CCER_CC1E;
3002  timer_set_oc_value(TIM4, TIM_OC1, pulse-1);
3003  }
3004 
3005  break;
3006 
3007  case CHANNEL_2:
3008 
3009  //Timer doesn't turn off completely at 0
3010  if(pulse == 0){
3011 
3012  TIM_CCER(TIM4) &= ~TIM_CCER_CC2E;
3013 
3014  }
3015  else{
3016 
3017  if(pulse > TIM_ARR(TIM4)){
3018 
3019  error = E_TIMER_PULSE;
3020  pulse = TIM_ARR(TIM4);
3021 
3022  if(MCU_debugIsEnabled()){
3023  MCU_printError(E_TIMER_PULSE);
3024  }
3025 
3026  }
3027  TIM_CCER(TIM4) |= TIM_CCER_CC2E;
3028  timer_set_oc_value(TIM4, TIM_OC2, pulse-1);
3029  }
3030  break;
3031 
3032  case CHANNEL_3:
3033  //Timer doesn't turn off completely at 0
3034  if(pulse == 0){
3035 
3036  TIM_CCER(TIM4) &= ~TIM_CCER_CC3E;
3037 
3038  }
3039  else{
3040 
3041  if(pulse > TIM_ARR(TIM4)){
3042 
3043  error = E_TIMER_PULSE;
3044  pulse = TIM_ARR(TIM4);
3045 
3046  if(MCU_debugIsEnabled()){
3047  MCU_printError(E_TIMER_PULSE);
3048  }
3049 
3050  }
3051  TIM_CCER(TIM4) |= TIM_CCER_CC3E;
3052  timer_set_oc_value(TIM4, TIM_OC3, pulse-1);
3053  }
3054  break;
3055 
3056  case CHANNEL_4:
3057 
3058  //Timer doesn't turn off completely at 0
3059  if(pulse == 0){
3060 
3061  TIM_CCER(TIM4) &= ~TIM_CCER_CC4E;
3062 
3063  }
3064  else{
3065 
3066  if(pulse > TIM_ARR(TIM4)){
3067 
3068  error = E_TIMER_PULSE;
3069  pulse = TIM_ARR(TIM4);
3070 
3071  if(MCU_debugIsEnabled()){
3072  MCU_printError(E_TIMER_PULSE);
3073  }
3074 
3075  }
3076  TIM_CCER(TIM4) |= TIM_CCER_CC4E;
3077  timer_set_oc_value(TIM4, TIM_OC4, pulse-1);
3078  }
3079  break;
3080  }
3081 
3082  break;
3083  default:
3084  if(MCU_debugIsEnabled()){
3085  MCU_printError(E_TIMER_NOTIMER);
3086  }
3087  error = E_TIMER_NOTIMER;
3088 
3089  break;
3090  }
3091 
3092  return error;
3093 
3094 }
3095 
3096 
3097 
PIN3
Pin 3 of the port.
Definition: stm32f103cb_gpio.h:112
PIN9
Pin 9 of the port.
Definition: stm32f103cb_gpio.h:118
TIMER_2
Timer 2.
Definition: stm32f103cb_timer.h:91
TIMER_setupPulse
mcu_error TIMER_setupPulse(timer_main timerNumber, timer_channel timerChannel, uint32_t frequency, uint32_t pulse)
Initialize given timer for Pulse mode.
Definition: stm32f103cb_timer.c:967
E_TIMER_PULSE
Error timer: Pulse too long.
Definition: stm32f103cb_debug.h:79
TIMER_setFrequency
mcu_error TIMER_setFrequency(timer_main timerNumber, uint32_t frequency)
Set the frequency for the timer. (in hertz)
Definition: stm32f103cb_timer.c:2344
TIMER_1
Timer 1.
Definition: stm32f103cb_timer.h:90
CHANNEL_4
Channel 4.
Definition: stm32f103cb_timer.h:104
E_TIMER_NOTIMER
Error timer: Timer doesn&#39;t exist.
Definition: stm32f103cb_debug.h:76
TIMER_3
Timer 3.
Definition: stm32f103cb_timer.h:92
TIMER_resume
mcu_error TIMER_resume(timer_main timerNumber)
Resume a paused timer.
Definition: stm32f103cb_timer.c:859
TIMER_pause
mcu_error TIMER_pause(timer_main timerNumber)
Pause an already running timer.
Definition: stm32f103cb_timer.c:825
TIMER_setCount
mcu_error TIMER_setCount(timer_main timerNumber, uint16_t count)
Set the current value of a running timer.
Definition: stm32f103cb_timer.c:2154
TIMER_setupCount
mcu_error TIMER_setupCount(timer_main timerNumber, uint32_t frequency, void(*handler)(void))
Initialize given timer for standard count with interrupt on timeout.
Definition: stm32f103cb_timer.c:1001
MCU_printError
void MCU_printError(mcu_error errorNum)
Print a given error number as a character stream.
Definition: stm32f103cb_debug.c:105
TIMER_enableISR
mcu_error TIMER_enableISR(timer_main timerNumber, void(*handler)(void))
Set the ISR target for timeout.
Definition: stm32f103cb_timer.c:696
TIMER_setPeriod
mcu_error TIMER_setPeriod(timer_main timerNumber, uint32_t period)
Set the period for the timer. (in microseconds)
Definition: stm32f103cb_timer.c:2193
PIN1
Pin 1 of the port.
Definition: stm32f103cb_gpio.h:110
MCU_debugIsEnabled
uint8_t MCU_debugIsEnabled(void)
Checks if debug is enabled.
Definition: stm32f103cb_debug.c:94
timer_main
timer_main
Main timers available on the MCU.
Definition: stm32f103cb_timer.h:88
TIMER_disableISR
mcu_error TIMER_disableISR(timer_main timerNumber)
Disable the timeout IRQ.
Definition: stm32f103cb_timer.c:751
CLOCK_getSpeed
uint32_t CLOCK_getSpeed(void)
Get the current clock speed of the device.
Definition: stm32f103cb_clock.c:57
PIN0
Pin 0 of the port.
Definition: stm32f103cb_gpio.h:109
PIN2
Pin 2 of the port.
Definition: stm32f103cb_gpio.h:111
CHANNEL_2
Channel 2.
Definition: stm32f103cb_timer.h:102
TIMER_setupPWM
mcu_error TIMER_setupPWM(timer_main timerNumber, timer_channel timerChannel, uint32_t frequency, uint8_t duty)
Initialize given timer for PWM mode.
Definition: stm32f103cb_timer.c:934
timer_channel
timer_channel
Timers channels available for each timer.
Definition: stm32f103cb_timer.h:99
PIN7
Pin 7 of the port.
Definition: stm32f103cb_gpio.h:116
PIN8
Pin 8 of the port.
Definition: stm32f103cb_gpio.h:117
CHANNEL_1
Channel 1.
Definition: stm32f103cb_timer.h:101
TIMER_setDuty
mcu_error TIMER_setDuty(timer_main timerNumber, timer_channel channel, uint8_t duty)
Set the duty cycle for the waveform (PWM only, 0 - 100%).
Definition: stm32f103cb_timer.c:2382
PIN6
Pin 6 of the port.
Definition: stm32f103cb_gpio.h:115
PORTB
Port B of the MCU.
Definition: stm32f103cb_gpio.h:87
pinSetup
mcu_error pinSetup(gpio_mode mode, gpio_port port, gpio_pin pin)
Setup a GPIO pin for a given function.
Definition: stm32f103cb_gpio.c:44
GPIO_PWM
Setup the port for output PWM.
Definition: stm32f103cb_gpio.h:64
TIMER_setPulse
mcu_error TIMER_setPulse(timer_main timerNumber, timer_channel channel, uint32_t pulse)
Set the pulse width for the output. (in microseconds)
Definition: stm32f103cb_timer.c:2653
TIMER_getCount
uint16_t TIMER_getCount(timer_main timerNumber)
Get the current value of a running timer.
Definition: stm32f103cb_timer.c:2119
stm32f103cb_timer.h
Header file for stm32f103cb timers.
E_TIMER_PERIOD
Error timer: Period too long / frequency too high.
Definition: stm32f103cb_debug.h:78
PIN11
Pin 11 of the port.
Definition: stm32f103cb_gpio.h:120
TIMER_setupIC
mcu_error TIMER_setupIC(timer_main timerNumber, timer_channel timerChannel)
Initialize given timer for input capture.
Definition: stm32f103cb_timer.c:897
TIMER_4
Timer 4.
Definition: stm32f103cb_timer.h:93
PIN10
Pin 10 of the port.
Definition: stm32f103cb_gpio.h:119
GPIO_IC
Setup the port for input capture.
Definition: stm32f103cb_gpio.h:65
E_TIMER_NOERROR
Error timer: No error.
Definition: stm32f103cb_debug.h:75
CHANNEL_3
Channel 3.
Definition: stm32f103cb_timer.h:103
E_TIMER_NOCHANNEL
Error timer: Channel doesn&#39;t exist.
Definition: stm32f103cb_debug.h:77
PORTA
Port A of the MCU.
Definition: stm32f103cb_gpio.h:86
mcu_error
mcu_error
Error enumerators for the Debug peripheral.
Definition: stm32f103cb_debug.h:44
TIMER_getIC
uint16_t TIMER_getIC(timer_main timerNumber, timer_channel channel)
Get the last input capture time from a channel of a timer.
Definition: stm32f103cb_timer.c:1442